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INTEGRATED CIRCUITS
DATA SHEET
SAA7185 Digital Video Encoder (DENC2)
Preliminary specification Supersedes data of 1995 Jun 15 File under Integrated Circuits, IC02 1996 Jul 08
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
FEATURES * CMOS 5 V device * Digital PAL/NTSC encoder * System pixel frequency 13.5 MHz * Accepts MPEG decoded data * 8-bit wide MPEG port * Input data format Cb, Y, Cr etc. (CCIR 656) * 16-bit wide YUV input port * I2C-bus control or alternatively MPU parallel control port * Encoder can be master or slave * Programmable horizontal and vertical input synchronization phase * Programmable horizontal sync output phase * OSD overlay with Look-Up Tables (LUTs) 8 x 3 bytes * Colour bar generator * Line 21 Closed Caption encoder * Cross-colour reduction * DACs operating at 27 MHz with 10-bit resolution * Controlled rise/fall times of output syncs and blanking * Down-mode of DACs * CVBS and S-Video output simultaneously * PLCC68 package. QUICK REFERENCE DATA SYMBOL VDDA VDDD IDDA IDDD Vi Vo(p-p) RL ILE DLE Tamb analog supply voltage digital supply voltage analog supply current digital supply current input signal voltage levels analog output signal voltages Y, C and CVBS without load - (peak-to-peak value) load resistance LF integral linearity error LF differential linearity error operating ambient temperature 80 - - 0 PARAMETER MIN. 4.75 4.5 - - TYP. 5.0 5.0 50 140 2 - - - - GENERAL DESCRIPTION
SAA7185
The SAA7185 encodes digital YUV video data to an NTSC, PAL CVBS or S-Video signal. The circuit accepts CCIR compatible YUV data with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG decoded data. It includes a sync/clock generator and on-chip Digital-to-Analog Converters (DACs). The circuit is compatible to the DIG-TV2 chip family.
MAX. 5.25 5.5 55 170 - - 2 1 +70 V V
UNIT
mA mA V LSB LSB C
TTL compatible
1996 Jul 08
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7185WP BLOCK DIAGRAM PLCC68 DESCRIPTION plastic leaded chip carrier; 68 leads
SAA7185
VERSION SOT188-2
KEY SEL_ED 18 MP7 to MP0 VP0 to VP7 20 to 27 8 9 to 16 8
OSD0 to OSD2 32 to 34
RTCI 43
VDDD1 to VDDD3 17,37,67
VDDA1 to VrefH VDDA4 II 47 55 48,50, 54,56 53 A 51 D 49 52 46
31
DATA MANAGER
ENCODER
OUTPUT INTERFACE
CVBS Y CHROMA VSSA VrefL
8
8 internal control bus
8
RCM1 RCM2
29 8 30 8 clock timing signals 8
SAA7185
CONTROL INTERFACE
SYNC CLK
1,8,19 28,35, 42,62
63 to 66 2 to 5
68
61 CS/SA
59
60
58
57
41 XTALI
40
38 LLC
39
36
6
7
MBE733
VSSD1 to VSSD7
DP0 to DP7
A0/SDA
RESET
CDIR Cref
RCV2
SEL_MPU
RW/SCL
DTACK
XTALO
RCV1
Fig.1 Block diagram.
1996 Jul 08
andbook, full pagewidth
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
PINNING SYMBOL VSSD1 DP4 DP5 DP6 DP7 RCV1 RCV2 VSSD2 VP0 VP1 VP2 VP3 VP4 VP5 VP6 VP7 VDDD1 SEL_ED VSSD3 MP7 MP6 MP5 MP4 MP3 MP2 MP1 MP0 VSSD4 RCM1 RCM2 KEY OSD0 OSD1 OSD2 VSSD5 CDIR VDDD2 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 digital ground 5 On-Screen Display data. This is the index for the internal OSD look-up table. digital ground 4 Raster Control 1 for MPEG port. This pin provides a VS/FS/FSEQ signal. MPEG Port. It is an input for CCIR 656 style multiplexed YUV data. digital supply voltage 1 digital ground 1 DESCRIPTION
SAA7185
Upper 4 bits of the Data Port. If pin 68 (SEL_MPU) is HIGH, this is the data bus of the parallel MPU interface. If it is LOW, they are the UV lines of the Video Port. Raster Control 1 for Video port. Depending on the synchronization mode, this pin receives/provides a VS/FS/FSEQ signal. Raster Control 2 for Video port. Depending on the synchronization mode, this pin receives/provides an HS/HREF/CBL signal. digital ground 2
Video Port. This is an input for CCIR 656 compatible, multiplexed video data. If the 16-bit DIG-TV2 format is used, this is the Y data.
Select Encoder Data. Selects data either from MPEG port or from video port as encoder input. digital ground 3
Raster Control 2 for MPEG port. This pin provides an HS pulse for the MPEG decoder. Key signal for OSD. It is active HIGH.
Clock direction. If the CDIR input is HIGH, the circuit receives a clock signal, otherwise LLC and CREF are generated by the internal crystal oscillator. digital supply voltage 2
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
SAA7185
SYMBOL LLC Cref XTALO XTALI VSSD6 RTCI AP SP VrefL VrefH VDDA1 CHROMA VDDA2 Y VSSA CVBS VDDA3 II VDDA4 RESET DTACK RW/SCL A0/SDA CS/SA VSSD7 DP0 DP1 DP2 DP3 VDDD3 SEL_MPU
PIN 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 digital supply voltage 3
DESCRIPTION Line-Locked Clock. This is the 27 MHz master clock for the encoder. The direction is set by the CDIR pin. Clock Reference signal. This is the clock qualifier for DIG-TV2 compatible signals. Crystal oscillator output (to crystal). Crystal oscillator input (from crystal). If the oscillator is not used, this pin should br connected to ground. digital ground 6 Real Time Control Input. If the clock is provided by an SAA7151B, RTCI should be connected to the RTCO pin of the decoder to improve the signal quality. Test pin. Connect to digital ground for normal operation. Test pin. Connect to digital ground for normal operation. Lower reference voltage input for the DACs. Upper reference voltage input for the DACs. Analog positive supply voltage 1 for the DACs and output amplifiers. Analog output of the chrominance signal. Analog supply voltage 2 for the DACs and output amplifiers. Analog output of the luminance signal. Analog ground for the DACs and output amplifiers. Analog output of the CVBS signal. Analog supply voltage 3 for the DACs and output amplifiers. Current input for the output amplifiers, connect via a 15 k resistor to VDDA. Analog supply voltage 4 for the DACs and output amplifiers. Reset input, active LOW. After reset is applied, all outputs are in 3-state input mode. The I2C-bus receiver waits for the start condition. Data acknowledge output of the parallel MPU interface, active LOW, otherwise high impedance. If pin 68 (SEL_MPU) is HIGH, this is the read/write signal of the parallel MPU interface, otherwise it is the I2C-bus serial clock input. If pin 68 (SEL_MPU) is HIGH, this is the address signal of the parallel MPU interface, otherwise it is the I2C-bus serial data input/output. If pin 68 (SEL_MPU) is HIGH, this is the chip select signal of the parallel MPU interface, otherwise it is the I2C-bus slave address select pin. LOW: slave address = 88H, HIGH = 8CH. digital ground 7 Lower 4 bits of the Data Port. If pin 68 (SEL_MPU) is HIGH, this is the data bus of the parallel MPU interface. If it is LOW, they are the UV lines of the Video Port.
Select MPU interface input. If it is HIGH, the parallel MPU interface is active, otherwise the I2C-bus interface will be used.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
SAA7185
59 RW/SCL
60 A0/SDA
handbook, full pagewidth
49 CHROMA
58 DTACK
57 RESET
56 VDDA4
54 VDDA3
50 VDDA2
48 VDDA1
VrefH
52 VSSA
53 CVBS
VrefL
45 SP
CS/SA 61 VSSD7 62 DP0 63 DP1 64 DP2 65 DP3 66 VDDD3 67 SEL_MPU 68 VSSD1 1 DP4 DP5 DP6 DP7 2 3 4 5
44 AP
51 Y
55 II
47
46
43 RTCI 42 VSSD6 41 XTALI 40 XTALO 39 Cref
38 LLC 37 VDDD2 36 CDIR
SAA7185
35 VSSD5 34 OSD2 33 OSD1 32 OSD0 31 KEY 30 RCM2 29 RCM1 28 VSSD4 27 MP0
RCV1 6 RCV2 VSSD2 VP0 7 8 9
VP1 10
VP2 11
VP3 12
VP4 13
VP5 14
VP6 15
VP7 16
VDDD1 17
SEL_ED 18
VSSD3 19
MP7 20
MP6 21
MP5 22
MP4 23
MP3 24
MP2 25
MP1 26
MBE732
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
FUNCTIONAL DESCRIPTION The digital MPEG-compatible Video Encoder (DENC2) encodes digital luminance and chrominance into analog CVBS and simultaneously S-Video (Y/C) signals. NTSC-M and PAL B/G standards also sub-standards are supported. The basic encoder function consists of subcarrier generation and colour modulation also insertion of synchronization signals. Luminance and chrominance signals are filtered in accordance with the standard requirements RS-170-A and CCIR 624. For ease of analog post filtering the signals are twice oversampled with respect to pixel clock before digital-to-analog conversion. For total filter transfer characteristics see Figs 3, 4, 5 and 6. The DACs are realized with full 10-bit resolution. The encoder provides three 8-bit wide data ports, that serve different applications. The MPEG Port (MP) and the Video Port (VP) accept 8 lines multiplexed Cb-Y-Cr data. The Video Port (VP) is also able to handle DIG-TV2 family compatible 16-bit YUV signals. In this event, the Data Port (DP) is used for the U/V components. The Data Port can handle the data of an 8-bit wide microprocessor interface, alternatively. The 8-bit multiplexed Cb-Y-Cr formats are CCIR 656 (D1 format) compatible, but the SAV, EAV etc. codes are not decoded. A crystal-stable master clock (LLC) of 27 MHz, which is twice the CCIR line-locked pixel clock of 13.5 MHz, needs to be supplied externally. Optionally, a crystal oscillator input/output pair of pins and an on-chip clock driver is provided. Additionally, a DMSD2 compatible clock interface, using Cref (input or output) and RTC (see "data sheet SAA7151B" ) is available. The DENC2 synthesizes all necessary internal signals, colour subcarrier frequency, and synchronization signals, from that clock. DENC2 is always timing master for the MPEG Port (MP), but it can additionally be configured as master or slave for the Video Port (VP). The IC also contains Closed Caption and Extended Data Services Encoding (Line 21); it also supports OSD via KEY and three-bit overlay techniques by a 24 x 8 LUT. The IC can be programmed via I2C-bus or 8-bit MPU interface, but only one interface configuration can be active at a time; if the 16-bit Video Port mode (VP and DP) is being used, only the I2C-bus interface can be selected.
SAA7185
A number of possibilities are provided for setting of different video parameters such as: black and blanking level control colour subcarrier frequency black variable burst amplitude etc. During reset (RESET = LOW) and after reset is released, all digital I/O stages are set to input mode. A reset forces the control interfaces to abort any running bus transfer and to set Register 3AH to contents 13H, Register 61H to contents 0X010101b, and Register 6CH to contents 00H. All other control registers are not influenced by a reset. Data manager In the Data manager, real time arbitration on the data stream to be encoded is performed. Depending on hardware conditions (signals on pins SEL_ED, KEY, OSD2 to OSD0, MP7 to to MP0, VP7 to VP0 and DP7 to DP0) and different software programming either data from the MP port, from the VP port, or from the OSD port are selected to be encoded to CVBS and Y/C signals. Optionally, the OSD colour look-up tables located in this block, can be read out in a pre-defined sequence (8 steps per active video line), achieving e.g. a colour bar test pattern generator without need for an external data source. The colour bar function is only under software control. Encoder VIDEO PATH The encoder generates out of Y, U and V baseband signals luminance and colour subcarrier output signals, suitable for use as CVBS or separate Y/C signals. Luminance is modified in gain and in offset (latter programmable in a certain range to enable different black level set-ups). After having been inserted a fixed synchronization level, in accordance with standard composite synchronization schemes, a variable blanking level, programmable also in a certain range, is inserted. In order to enable easy analog post filtering, luminance is interpolated from 13.5 MHz data rate to 27 MHz data rate, providing luminance in 10-bit resolution. This filter is also used to define smoothed transients for synchronization pulses and blanking period. For transfer characteristic of the luminance interpolation filter see Figs 5 and 6.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
Chrominance is modified in gain (programmable separately for U and V), standard dependent burst is inserted, before baseband colour signals are interpolated from 6.75 MHz data rate to 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for Y/C output. For transfer characteristics of the chrominance interpolation filter see Figs 3 and 4. The amplitude of inserted burst is programmable in a certain range, suitable for standard signals and for special effects. Behind the succeeding quadrature modulator, colour in 10-bit resolution is provided on subcarrier. The numeric ratio between Y and C outputs is in accordance with set standards. CLOSED CAPTION ENCODER Using this circuit, data in accordance with the specification of Closed Caption or Extended Data Service, delivered by the control interface, can be encoded (Line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. The actual line number where data is to be encoded in, can be modified in a certain range. Data clock frequency is in accordance with definition for NTSC-M standard 32 times horizontal line frequency. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 . It is also possible to encode Closed Caption Data for 50 Hz field frequencies at 32 times horizontal line frequency. Output Interface In the output interface encoded Y and C signals are converted from digital-to-analog in 10-bit resolution both Y and C signals are combined to a 10-bit CVBS signal, also; in front of the summation point, the luminance signal can optionally be fed through a further filter stage, suppressing components in the range of subcarrier frequency. Thus, a type of Cross Colour reduction is provided, which is useful in a standard TV set with CVBS input. Slopes of synchronization pulses are not affected with any Cross Colour reduction active. Three different filter characteristics or bypass are available, see Fig.5.
SAA7185
The CVBS output occurs with the same processing delay as the Y and C outputs. Absolute amplitudes at the input of the DAC for CVBS is reduced by 1516 with respect to Y and C DACs to make maximum use of conversion ranges. Outputs of all DACs can be set together via software control to minimum output voltage for either purpose. Synchronization The synchronization of the DENC2 is able to operate in two modes; slave mode and master mode. In the slave mode, the circuit accepts synchronization pulses at the bidirectional RCV1 port. The timing and trigger behaviour related to the video signal on VP (and DP, if used) can be influenced by programming the polarity and on-chip delay of RCV1. Active slope of RCV1 defines the vertical phase and optionally the odd/even and colour frame phase to be initialized, it can be also used to set the horizontal phase. If the horizontal phase is not be influenced by RCV1, a horizontal pulse needs to be supplied at the RCV2 pin. Timing and trigger behaviour can also be influenced for RCV2. If there are missing pulses at RCV1 and/or RCV2, the time base of DENC2 runs free, thus an arbitrary number of synchronization slopes may miss, but no additional pulses (such with wrong phase) must occur. If the vertical and horizontal phase is derived from RCV1, RCV2 can be used for horizontal or composite blanking input or output. In the master mode, the time base of the circuit continuously runs free. On the RCV1 port, the IC can output: * A Vertical Sync signal (VS) with 3 or 2.5 lines duration, or * An ODD/EVEN signal which is LOW in odd fields, or * A field sequence signal (FSEQ) which is HIGH in the first of 4 respectively 8 fields. On the RCV2 port, the IC can provide a horizontal pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up e.g. a composite blanking signal. The phase of the pulses output on RCV1 or RCV2 are referenced to the VP port, polarity of both signals is selectable.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
The DENC2 is always the timing master for the source at the MP input. The IC provides two signals for synchronizing this source: On the RCM1 port the same signals as on RCV1 (as output) are available; on RCM2 the IC provides a horizontal pulse with programmable start and stop phase. The length of a field also start and end of its active part can be programmed. The active part of a field always starts at the beginning of a line. Control interface DENC2 contains two control interfaces: an I2C-bus slave transceiver and 8-bit parallel microprocessor interface. The interfaces cannot be used simultaneously. The interface is a standard slave transceiver, supporting 7-bit slave addresses and 100 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write only, except one readable status byte. Two I2C-bus slave addresses can be selected (pin SEL_MPU must be LOW): 88H: LOW at pin 61 8CH: HIGH at pin 61. The parallel interface is defined by: D7 to D0 data bus CS active-LOW chip select signal RW read/not write signal, LOW for a write cycle DTACK 680xx style data acknowledge (handshake), active-LOW A0 register select, LOW selects address, HIGH selects data. The parallel interface uses two registers, one auto-incremental containing the current address of a control register (equals subaddress with I2C-bus control), one containing actual data. The currently addressed register is mapped to the corresponding control register. The status byte can be read optionally via a read access to the address register, no other read access is provided. I2C-bus Input levels and formats
SAA7185
DENC2 expects digital YUV data with levels (digital codes) in accordance with CCIR 601. Deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. The MPEG port accepts only 8-bit multiplexed CCIR 656 compatible data. If the I2C-bus interface is used, the VP port can handle both formats, 8-bit multiplexed Cb-Y-Cr data on the VP lines, or the 16-bit DTV2 format with the Y signal on the VP lines and the UV signal on the DP port. Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
Table 1 CCIR signal component levels IRE 0 Y 50 100 bottom peak Cb colourless top peak bottom peak Cr colourless top peak Table 2 8-bit multiplexed format (similar to CCIR 656) TIME Sample Luminance pixel number Colour pixel number Table 3 16-bit multiplexed format (DTV2 format) TIME Sample Y line Sample UV line Luminance pixel number Colour pixel number 0 Y0 Cb0 0 0 1 2 Y1 Cr0 1 3 4 Y2 Cb2 2 2 5 0 Cb0 0 0 1 Y0 2 Cr0 1 2 Y1 4 Cb2 2 2 5 Y2 DIGITAL LEVEL 16 126 235 16 128 240 16 128 240
SAA7185
SIGNAL
CODE straight binary
straight binary
straight binary
6 Cr2 3
7 Y3
6 Y3 Cr2 3
7
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10
Bit allocation map
Table 4 DATA BYTE (note 1) D7 0 0 CBENB OSDY07 OSDU07 OSDV07 OSDY77 OSDU77 OSDV77 CHPS7 GAINU7 GAINV7 GAINU8 GAINV8 0 CCRS1 0 SQP FSC07 FSC15 FSC23 FSC31 L21O07 L21O17 L21E07 L21E17 MODIN1 L21O06 L21O16 L21E06 L21E16 MODIN0 FSC30 FSC22 FSC14 FSC06 FSC05 FSC13 FSC21 FSC29 L21O05 L21O15 L21E05 L21E15 0 BSTA6 BSTA5 DOWN INPI1 CCRS0 0 0 YGS BSTA4 FSC04 FSC12 FSC20 FSC28 L21O04 L21O14 L21E04 L21E14 SCCLN4 0 0 0 0 BLNNL5 BLNNL4 0 BLCKL5 BLCKL4 GAINV6 GAINV5 GAINV4 GAINV3 BLCKL3 BLNNL3 0 0 RTCE BSTA3 FSC03 FSC11 FSC19 FSC27 L21O03 L21O13 L21E03 L21E13 SCCLN3 GAINU6 GAINU5 GAINU4 GAINU3 CHPS6 CHPS5 CHPS4 CHPS3 OSDV76 OSDV75 OSDV74 OSDV73 CHPS2 GAINU2 GAINV2 BLCKL2 BLNNL2 0 0 SCBW BSTA2 FSC02 FSC10 FSC18 FSC26 L21O02 L21O12 L21E02 L21E12 SCCLN2 OSDU76 OSDU75 OSDU74 OSDU73 OSDU72 OSDV72 OSDY76 OSDY75 OSDY74 OSDY73 OSDY72 OSDY71 OSDU71 OSDV71 CHPS1 GAINU1 GAINV1 BLCKL1 BLNNL1 0 0 PAL BSTA1 FSC01 FSC09 FSC17 FSC25 L21O01 L21O11 L21E01 L21E11 SCCLN1 OSDY70 OSDU70 OSDV70 CHPS0 GAINU0 GAINV0 BLCKL0 BLNNL0 0 0 FISE BSTA0 FSC00 FSC08 FSC16 FSC24 L21O00 L21O10 L21E00 L21E10 SCCLN0 OSDV06 OSDV05 OSDV04 OSDV03 OSDV02 OSDV01 OSDU06 OSDU05 OSDU04 OSDU03 OSDU02 OSDU01 OSDY06 OSDY05 OSDY04 OSDY03 OSDY02 OSDY01 0 0 V656 VY2C VUV2C MY2C 0 0 0 0 0 0 0 MUV2C OSDY00 OSDU00 OSDV00 0 0 0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0
1996 Jul 08
Slave Receiver (Slave Address 88H or 8CH)
REGISTER FUNCTION
SUB ADDRESS
Null
00
Philips Semiconductors
Null
39
Input port control
3A
OSD LUT Y0
42
OSD LUT U0
43
OSD LUT V0
44
Digital Video Encoder (DENC2)
OSD LUT Y7
57
OSD LUT U7
58
OSD LUT V7
59
Chrominance phase
5A
11
Gain U
5B
Gain V
5C
Gain U MSB, black level
5D
Gain V MSB, blanking level
5E
Null
5F
Cross-colour select
60
Standard control
61
Burst amplitude
62
Subcarrier 0
63
Subcarrier 1
64
Subcarrier 2
65
Subcarrier 3
66
Line 21 odd 0
67
Line 21 odd 1
68
Line 21 even 0
69
SAA7185
Line 21 even 1
6A
Preliminary specification
Encoder control, CC line
6B
DATA BYTE (note 1) D7 SRCV11 0 HTRIG7 0 PHRES1 BMRQ7 EMRQ7 0 0 0 0 BRCV7 ERCV7 0 FLEN7 FAL7 LAL7 0 0 LAL8 FAL8 LAL6 LAL5 LAL4 LAL3 0 FAL6 FAL5 FAL4 FAL3 FLEN6 FLEN5 FLEN4 FLEN3 ERCV10 ERCV09 ERCV08 0 ERCV6 ERCV5 ERCV4 ERCV3 ERCV2 BRCV10 FLEN2 FAL2 LAL2 0 BRCV6 BRCV5 BRCV4 BRCV3 BRCV2 0 0 0 0 0 0 0 0 0 0 0 0 BRCV1 ERCV1 BRCV09 FLEN1 FAL1 LAL1 FLEN9 0 0 0 0 0 0 EMRQ10 EMRQ09 EMRQ08 0 BMRQ10 BMRQ09 EMRQ6 EMRQ5 EMRQ4 EMRQ3 EMRQ2 EMRQ1 BMRQ6 BMRQ5 BMRQ4 BMRQ3 BMRQ2 BMRQ1 PHRES0 SBLBN VTRIG4 VTRIG3 VTRIG2 VTRIG1 VTRIG0 BMRQ0 EMRQ0 BMRQ08 0 0 0 BRCV0 ERCV0 BRCV08 FLEN0 FAL0 LAL0 FLEN8 0 0 0 0 HTRIG10 HTRIG09 HTRIG08 HTRIG6 HTRIG5 HTRIG4 HTRIG3 HTRIG2 HTRIG1 HTRIG0 0 0 0 SRCM11 SRCM10 CCEN1 CCEN0 SRCV10 TRCV2 ORCV1 PRCV1 CBLF ORCV2 PRCV2 D6 D5 D4 D3 D2 D1 D0
REGISTER FUNCTION
SUB ADDRESS
1996 Jul 08
RCV port control
6C
RCM, CC mode
6D
Horizontal trigger
6E
Philips Semiconductors
Horizontal trigger
6F
fsc reset mode, Vertical trigger
70
Begin MP request
71
End MP request
72
MSBs MP request
73
Null
74
Null
75
Digital Video Encoder (DENC2)
Null
76
Begin RCV2 output
77
End RCV2 output
78
MSBs RCV2 output
79
12
Field length
7A
First active line
7B
Last active line
7C
MSBs field control
7D
Note
1. All bits labelled `0' are reserved. They must be programmed with logic 0.
Preliminary specification
SAA7185
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
I2C-bus format Table 5 S Table 6 I2C-bus address; see Table 6 SLAVE ADDRESS ACK SUBADDRESS ACK DATA 0 ACK --------
SAA7185
DATA n
ACK
P
Explanation of Table 5 PART DESCRIPTION START condition 1 0 0 0 1 0 0 X or 1 0 0 0 1 1 0 X (note 1) acknowledge, generated by the slave subaddress byte data byte continued data bytes and ACKs STOP condition
S Slave address ACK Subaddress (note 2) DATA -------P Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read, no subaddressing with read. 2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed. Slave Receiver Table 7 Subaddress 3A LOGIC LEVEL 0 1 MY2C VUV2C VY2C V656 CBENB 0 1 0 1 0 1 0 1 0 1 DESCRIPTION Cb/Cr data at MP are two's complement. Cb/Cr data at MP are straight binary. Default after reset. Y data at MP are two's complement. Y data at MP are straight binary. Default after reset. Cb/Cr data input to VP or DP are two's complement. Default after reset. Cb/Cr data input to VP or DP are straight binary. Y data input to VP are two's complement. Default after reset. Y data input to VP are straight binary. Selects YUV 422 format on VP (8 lines Y) and DP (8 lines multiplexed Cb/Cr). Selects CCIR 656 compatible format on VP (8 lines Cb, Y, Cr). Default after reset. Data from input ports are encoded. Default after reset. Colour bar with programmable colours (entries of OSD_LUTs) is encoded. The LUTs are read in upward order from index 0 to index 7.
DATA BYTE MUV2C
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
Table 8 Subaddress 42 to 59 DATA BYTE (note 1) COLOUR OSDY White Yellow Cyan Green Magenta Red Blue Black 107 (6BH) 107 (6BH) 82 (52H) 34 (22H) 42 (2AH) 03 (03H) 17 (11H) 240 (F0H) 234 (EAH) 212 (D4H) 209 (D1H) 193 (C1H) 169 (A9H) 163 (A3H) 144 (90H) 144 (90H) Notes OSDU 0 (00H) 0 (00H) 144 (90H) 172 (ACH) 38 (26H) 29 (1DH) 182 (B6H) 200 (C8H) 74 (4AH) 56 (38H) 218 (DAH) 227 (E3H) 112 (70H) 84 (54H) 0 (00H) 0 (00H) OSDV 0 (00H) 0 (00H) 18 (12H) 14 (0Eh) 144 (90H) 172 (ACH) 162 (A2H) 185 (B9H) 94 (5EH) 71 (47H) 112 (70H) 84 (54H) 238 (EEH) 242 (F2H) 0 (00H) 0 (00H)
SAA7185
INDEX (note 2) 0 1 2 3 4 5 6 7
1. Contents of OSD Look-up tables. All 8 entries are 8-bits. Data representation is in accordance with CCIR 601 (Y, Cb, Cr), but two's complement, e.g. for a 100100 (upper number) or 10075 (lower number) colour bar. 2. For normal colour bar with CBENB = logic 1. Table 9 Subaddress 5A DESCRIPTION Phase of encoded colour subcarrier (including burst) relative to horizontal sync. Can be adjusted in steps of 360/256 degrees.
DATA BYTE CHPS
Table 10 Subaddress 5B and 5D DATA BYTE GAINU DESCRIPTION CONDITIONS IRE(1) output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal REMARKS
variable gain for Cb signal; white-to-black = 92.5 input representation GAINU = 0 accordance with CCIR 601 GAINU = 118 (76H) white-to-black = 100 GAINU = 0
IRE(2)
GAINU = 125 (7DH) Notes 1. GAINU = -2.17 x nominal to +2.16 x nominal. 2. GAINU = -2.05 x nominal to +2.04 x nominal.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
Table 11 Subaddress 5C and 5E DATA BYTE GAINV DESCRIPTION CONDITIONS REMARKS
SAA7185
variable gain for Cr signal; white-to-black = 92.5 IRE(1) input representation GAINV = 0 accordance with CCIR 601 GAINV = 165 (A5H) white-to-black = 100 GAINV = 0 GAINV = 175 (AFH) IRE(2)
output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal
Notes 1. GAINV = -1.55 x nominal to +1.55 x nominal. 2. GAINV = -1.46 x nominal to +1.46 x nominal. Table 12 Subaddress 5D DATA BYTE BLCKL DESCRIPTION CONDITIONS REMARKS output black level = 24 IRE output black level = 49 IRE output black level = 24 IRE output black level = 50 IRE
variable black level; input white-to-sync = 140 IRE(1) representation accordance BLCKL = 0 with CCIR 601 BLCKL = 63 (3FH) white-to-sync = 143 IRE(2) BLCKL = 0 BLCKL = 63 (3FH)
Notes 1. Output black level/IRE = BLCKL x 25/63 + 24; recommended value: BLCKL = 60 (3CH) normal. 2. Output black level/IRE = BLCKL x 26/63 + 24; recommended value: BLCKL = 45 (2DH) normal. Table 13 Subaddress 5E DATA BYTE BLNNL DESCRIPTION variable blanking level CONDITIONS white-to-sync = 140 IRE(1) BLNNL = 0 BLNNL = 63 (3FH) white-to-sync = 143 IRE(2) BLNNL = 0 BLNNL = 63 (3FH) Notes 1. Output black level/IRE = BLNNL x 25/63 + 17; recommended value: BLNNL = 58 (3AH) normal. 2. Output black level/IRE = BLNNL x 26/63 + 17; recommended value: BLNNL = 63 (3FH) normal. output blanking level = 17 IRE output blanking level = 43 IRE output blanking level = 17 IRE output blanking level = 42 IRE REMARKS
1996 Jul 08
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
Table 14 Subaddress 60 (CCRS; select cross colour reduction filter in luminance) DATA BYTE FUNCTION CCRS1 0 0 1 1 CCRS0 0 1 0 1
SAA7185
no cross colour reduction (for overall transfer characteristic of luminance see Fig.5) cross colour reduction #1 active (for overall transfer characteristic see Fig.5) cross colour reduction #2 active (for overall transfer characteristic see Fig.5) cross colour reduction #3 active (for overall transfer characteristic see Fig.5)
Table 15 Subaddress 61 DATA BYTE FISE PAL SCBW LOGIC LEVEL 0 1 0 1 0 1 RTCE 0 1 YGS 0 1 INPI DOWN 0 1 0 1 864 total pixel clocks per line 858 total pixel clocks per line; default after reset NTSC encoding (non-alternating V component); default after reset PAL encoding (alternating V component) enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4) standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4); default after reset no real time control of generated subcarrier frequency; default after reset real time control of generated subcarrier frequency through SAA7151B (timing see Fig.9) luminance gain for white - black 100 IRE luminance gain for white - black 92.5 IRE including 7.5 IRE set-up of black; default after reset PAL switch phase is nominal; default after reset PAL switch phase is inverted compared to nominal DACs in normal operational mode (not defined after reset, program after all zero-bits are set to zero) DACs forced to lowest output voltage (not defined after reset, program after all zero-bits are set to zero) DESCRIPTION
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
Table 16 Subaddress 62 DATA BYTE BSTA DESCRIPTION amplitude of colour burst; input representation accordance with CCIR 601 CONDITIONS white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding BSTA = 0 to 1.25 x nominal(1) white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding BSTA = 0 to 1.76 x nominal(2) white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding BSTA = 0 to 1.20 x nominal(3) white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 1.67 x nominal(4) SQP subcarrier real time logic 0 logic 1 Notes 1. Recommended value: BSTA = 102 (66H). 2. Recommended value: BSTA = 72 (48H). 3. Recommended value: BSTA = 106 (6AH). 4. Recommended value: BSTA = 75 (4BH). Table 17 Subaddress 63 to 66 (four bytes to program subcarrier frequency) DATA BYTE DESCRIPTION CONDITIONS
SAA7185
REMARKS
control from SAA7151B digital colour decoder not supported in current version, do not use
REMARKS FSC3 = most significant byte FSC0 = least significant byte
FSC0 to FSC3 ffsc = subcarrier frequency f fsc 32 FSC = round ------- x 2 (in multiples of line f llc frequency); fllc = clock frequency (in see note 1 multiples of line frequency) Notes 1. Examples:
a) NTSC-M: ffsc = 227.5 MHz, fllc = 1716 MHz FSC = 569408543 (21F07C1FH). b) PAL-B/G: ffsc = 283.7516 MHz, fllc = 1728 MHz FSC = 705268427 (2A098ACBH).
1996 Jul 08
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
Table 18 Subaddress 67 to 6A DATA BYTE(1) L21O0 L21O1 L21E0 L21E1 Note first byte of captioning data, odd field second byte of captioning data, odd field first byte of extended data, even field second byte of extended data, even field DESCRIPTION
SAA7185
1. LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of line 21 encoding format. Table 19 Subaddress 6B DATA BYTE SCCLN MODIN Note 1. Line = (SCCLN + 4) for M systems; line = (SCCLN + 1) for other systems. Table 20 Logic levels and function of MODIN DATA BYTE FUNCTION MODIN1 0 0 1 1 MODIN0 0 1 0 1 unconditionally from MP port from MP port, if pin SEL_ED = HIGH; otherwise from VP port unconditionally from VP port from VP port, if pin SEL_ED = HIGH; otherwise from MP port DESCRIPTION selects the actual line, where closed caption or extended data are encoded; see note 1 defines video data of MP port or VP(DP) port to be encoded; see Table 20
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
Table 21 Subaddress 6C DATA BYTE PRCV2 LOGIC LEVEL 0 1 ORCV2 CBLF 0 1 0 DESCRIPTION
SAA7185
polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively; default after reset polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively pin RCV2 is switched to input; default after reset pin RCV2 is switched to output if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference Pulse that is HIGH during active portion of line, also during vertical blanking Interval); default after reset if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization only (if TRCV2 = 1); default after reset if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization (if TRCV2 = 1) also as an internal blanking signal
1
PRCV1
0 1
polarity of RCV1 as output is active HIGH, rising edge is taken when input, respectively; default after reset polarity of RCV1 as output is active LOW, falling edge is taken when input, respectively pin RCV1 is switched to input; default after reset pin RCV1 is switched to output horizontal synchronization is taken from RCV1 port; default after reset horizontal synchronization is taken from RCV2 port defines signal type on pin RCV1; see Table 22
ORCV1 TRCV2 SRCV1
0 1 0 1 -
Table 22 Logic levels and function of SRCV1 DATA BYTE AS OUTPUT SRCV11 0 0 1 1 SRCV10 0 1 0 1 VS FS FSEQ - VS FS FSEQ - Vertical Sync each field; default after reset Frame Sync (odd/even) Field Sequence, vertical sync every fourth field (FISE = 1) or eighth field (FISE = 0) not applicable AS INPUT FUNCTION
Table 23 Subaddress 6D DATA BYTE CCEN SRCM DESCRIPTION enables individual line 21 encoding; see Table 24 defines signal type on pin RCM1; see Table 25
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
Table 24 Logic levels and function of CCEN DATA BYTE FUNCTION CCEN1 0 0 1 1 CCEN0 0 1 0 1 line 21 encoding OFF enables encoding in field 1 (odd) enables encoding in field 2 (even) enables encoding in both fields
SAA7185
Table 25 Logic levels and function of SRCM DATA BYTE AS OUTPUT SRCM1 0 0 1 1 SRCM0 0 1 0 1 VS FS FSEQ - Vertical Sync each field Frame Sync (odd/even) Field Sequence, vertical sync every fourth field (FISE = 1) or eighth field (FISE = 0) not applicable FUNCTION
Table 26 Subaddress 6E to 6F DATA BYTE HTRIG DESCRIPTION sets the Horizontal Trigger phase related to signal on RCV1 or RCV2 input values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed increasing HTRIG decreases delays of all internally generated timing signals reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used for triggering at HTRIG = 032H Table 27 Subaddress 70 DATA BYTE VTRIG LOGIC LEVEL - DESCRIPTION sets the Vertical TRIGger phase related to signal on RCV1 input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines variation range of VTRIG = 0 to 31 (1FH) SBLBN 0 1 PHRES Note 1. If cross-colour reduction is programmed, it is active between FAL and LAL in both events. - vertical blanking is defined by programming of FAL and LAL vertical blanking is forced automatically at least during field synchronization and equalization pulses; note 1 selects the phase reset mode of the colour subcarrier generator; see Table 28
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
Table 28 Logic levels and function of PHRES DATA BYTE FUNCTION PHRES1 0 0 1 1 PHRES0 0 1 0 1 no reset reset every two lines reset every eight fields reset every four fields
SAA7185
Table 29 Subaddress 71 to 73 DATA BYTE BMRQ beginning of MP ReQuest signal (RCM2) values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed first active pixel at analog outputs (corresponding input pixel coinciding with RCM2) at BMRQ = 0F9H (115H) EMRQ end of MP ReQuest signal (RCM2) values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with RCM2) at EMRQ = 686H (690H) Table 30 Subaddress 77 to 79 DATA BYTE BRCV beginning of output signal on RCV2 pin values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at BRCV = 0F9H (115H) ERCV end of output signal on RCV2 pin values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at ERCV = 686H (690H) Table 31 Subaddress 7A to 7D DATA BYTE FLEN DESCRIPTION Length of a Field = FLEN + 1, measured in half lines valid range is limited to 524 to 1022 (FISE = 1) respectively 624 to 1022 (FISE = 0), FLEN should be even FAL LAL First Active Line after vertical blanking interval = FAL + 1, measured in lines FAL = 0 coincides with the first field synchronization pulse Last Active Line before vertical blanking interval = LAL + 1, measured in lines LAL = 0 coincides with the first field synchronization pulse SUBADDRESSES In subaddresses 5B, 5C, 5D, 5E and 62 all IRE values are rounded up. DESCRIPTION DESCRIPTION
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
Slave Transmitter Table 32 Slave Transmitter (slave address 89H or 8DH) REGISTER FUNCTION Status byte Table 33 No subaddress DATA BYTE VER CCRDE DESCRIPTION DATA BYTE SUBADDRESS D7 - VER2 D6 VER1 D5 VER0 D4 D3 D2 FSQ2
SAA7185
D1 FSQ1
D0 FSQ0
CCRDE CCRDO
Version identification of the device. It will be changed with all versions of the IC that have different programming models. Current Version is 000 binary. Closed caption bytes of the even field have been encoded. The bit is reset after information has been written to the subaddresses 69 and 6A. It is set immediately after the data have been encoded.
CCRDO
Closed caption bytes of the odd field have been encoded. The bit is reset after information has been written to the subaddresses 67 and 68. It is set immediately after the data have been encoded.
FSQ
State of the internal field sequence counter. Bit 0 (FSQ0) gives the odd/even information; odd = LOW, even = HIGH.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
SAA7185
handbook, full pagewidth 6
MBE737
Gv
(dB)
0 -6
-12 -18 -24
(1) (2)
-30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14
(1) SCBW = 1. (2) SCBW = 0.
Fig.3 Chrominance transfer characteristic 1.
handbook, halfpage
2
MBE735
Gv (dB) 0
(1)
(2)
-2
-4
-6
0
0.4
0.8
1.2
f (MHz)
1.6
(1) SCBW = 1. (2) SCBW = 0.
Fig.4 Chrominance transfer characteristic 2.
1996 Jul 08
23
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
SAA7185
Gv handbook, full pagewidth (dB)
(4)
6 0
MBE738
(2)
-6 -12 -18 -24
(3)
(1)
-30 -36 -42 -48 -54 0 (1) (2) (3) (4) CCRS1 = 0; CCRS0 = 1. CCRS1 = 1; CCRS0 = 0. CCRS1 = 1; CCRS0 = 1. CCRS1 = 0; CCRS0 = 0. 2 4 6 8 10 12 f (MHz) 14
Fig.5 Luminance transfer characteristic 1.
handbook, halfpage
MBE736
1
Gv (dB) 0
-1 -2
-3 -4 -5
0
2
4
f (MHz)
6
CCRS1 = 0; CCRS0 = 0.
Fig.6 Luminance transfer characteristic 2
1996 Jul 08
24
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
CHARACTERISTICS VDDD = 4.5 to 5.5 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL Supply VDDD VDDA IDDD IDDA Inputs VIL VIH LOW level input voltage (except LLC, SDA, SCL, AP, SP and XTALI) HIGH level input voltage (except LLC, SDA, SCL, AP, SP and XTALI) HIGH level input voltage (LLC) VLI CI input leakage current input capacitance clocks operating data available I/Os at high impedance Outputs VOL VOH LOW level output voltage (except SDA and XTALO) HIGH level output voltage (except LLC, SDA, DTACK and XTALO) HIGH level output voltage (LLC) I2C-bus; VIL VIH II VOL IO TLLC tr tf SDA and SCL LOW level input voltage HIGH level input voltage input current LOW level output voltage (SDA) output current VI = LOW or HIGH IOL = 3 mA during acknowledge -0.5 3.0 -10 - 3 note 2 note 2 note 2 0 2.4 2.6 0.6 -0.5 2.0 2.4 - - - - digital supply voltage analog supply voltage digital supply current analog supply current note 1 note 1 4.5 4.75 - - 5.5 PARAMETER CONDITIONS MIN.
SAA7185
MAX.
UNIT
V V mA mA
5.25 170 55
+0.8
V
VDDD + 0.5 V VDDD + 0.5 V 1 10 8 8 A pF pF pF
V
VDDD + 0.5 V VDDD + 0.5 V
+1.5 +10 0.4 -
V A V mA
VDDD + 0.5 V
Clock timing (LLC) cycle time duty factor tHIGH/TLLC rise time fall time note 3 note 4 note 3 note 3 34 40 - - 41 60 5 6 ns % ns ns
1996 Jul 08
25
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
SAA7185
SYMBOL Input timing tSU;CREF tHD;CREF tSU
PARAMETER
CONDITIONS
MIN. - - -
MAX.
UNIT
input data set-up time (Cref) input data hold time (Cref) input data set-up time (any other except SEL_MPU, CDIR, RW/SCL, A0/SDA, CS/SA, RESET, AP and SP) input data hold time (any other except SEL_MPU, CDIR, RW/SCL, A0/SDA, CS/SA, RESET, AP and SP)
6 3 6
ns ns ns
tHD
3
-
ns
Crystal oscillator fn f/fn Tamb CL RS C1 C0 tAS tAH tRWS tRWH tDD tDF tDS tDH tACS tCSD tDAT CL tOH tOD nominal frequency (usually 27 MHz) permissible deviation of nominal frequency 3rd harmonic note 5 - -50 0 8 - 1.5 -20% 3.5 -20% 30 +50 MHz 10-6 C pF fF pF
CRYSTAL SPECIFICATION operating ambient temperature load capacitance series resistance motional capacitance (typical) parallel capacitance (typical) 70 - 80 1.5 +20% 3.5 +20% - - - - 400 255 - - 475 - 330
MPU interface timing address set-up time address hold time read/write set-up time read/write hold time data bus floating from CS (read) data valid from CS (read) data bus set-up time (write) data bus hold time (write) acknowledge delay from CS CS HIGH from acknowledge DTACK floating from CS HIGH notes 7 and 8; n = 7 notes 7, 8 and 9; n = 9 notes 7 and 8; n = 5 note 6 note 6 notes 7 and 8; n = 11 note 6 note 6 9 0 9 0 - - 9 9 - 0 - ns ns ns ns ns ns ns ns ns ns ns
Data and reference signal output timing output load capacitance output hold time output delay time Cref in output mode 7.5 4 - 40 - 25 pF ns ns
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
SAA7185
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
CHROMA, Y and CVBS outputs Vo(p-p) RI RL B ILE DLE Notes 1. At maximum supply voltage with highly active input signals. 2. The levels have to be measured with load circuits of 1.2 k to 3.0 V (standard TTL load) and CL = 25 pF. 3. The data is for both input and output direction. 4. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%. 5. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 6. The value is calculated via equation t = t SU + t HD 7. The value depends on the clock frequency. The numbers given are calculated with fLLC = 27 MHz. 8. The values given are calculated via equation t dmax = t OD + n x t LLC + t LLC + t SU 9. The falling edge of DTACK will always occur1 x LLC after data is valid. 10. For full digital range, without load, VDDA = 5.0 V. The typical voltage swing is 2.0 V, the typical minimum output voltage (digital zero at DAC) is 0.2 V. output signal voltage (peak-to-peak value) internal serial resistance output load resistance output signal bandwidth of DACs LF integral linearity error of DACs LF differential linearity error of DACs -3 dB note 10 1.9 18 80 10 - - 2.1 35 - - 2 1 V MHz LSB LSB
1996 Jul 08
27
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
SAA7185
handbook, full pagewidth
tHIGH
TLLC 2.6 V 1.5 V 0.6 V
LLC clock output tHD; DAT tHIGH LLC clock input tf TLLC tr
2.4 V 1.5 V 0.8 V tSU; DAT tHD; DAT tf tr 2.0 V
input data
valid td
not valid
valid 0.8 V
tHD; DAT output data valid
2.4 V not valid valid 0.6 V
MBE742
Fig.7 Clock data timing.
handbook, full pagewidth
LLC
CREF
VP(n)
Y(0)
Y(1)
Y(2)
Y(3)
Y(4)
DP(n)
Cb(0)
Cr(0)
Cb(2)
Cr(2)
Cb(4)
RCV2
MBE739
The data demultiplexing phase is coupled to the internal horizontal phase. The Cref signal applies only for the 16 lines digital TV format, because these signals are only valid in 13.5 MHz. The phase of the RCV2 signal is programmed to 0F8h (115H for 50 Hz) in this example in output mode (BRCV2).
Fig.8 Digital TV timing.
1996 Jul 08
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
SAA7185
handbook, full pagewidth
H/L transition count start 128 13
HPLL increment
4 bits reserved 0 21
5 bits reserved 0
sequence bit (1) reserved (2)
RTCI
not used in DENC2
valid invalid sample sample
8/LLC
MBE743
(1) Sequence bit: PAL = logic 0 then (R - Y) line normal; PAL = logic 1 then (R - Y) line inverted. NTSC = logic 0 then no change. (2) Reserved bits: 236 with 50 Hz systems; 233 with 60 Hz systems.
Fig.9 RTCI timing.
handbook, full pagewidth
A0 tAS tAH
CSN
RWN tRWS tRWH
D(7 to 0) tDD tDF
DTACK tACS tCSD tDAT
MBE740
Fig.10 MPU interface timing (READ cycle).
1996 Jul 08
29
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
SAA7185
handbook, full pagewidth
A0 tAS tAH
CSN
RWN tRWS tRWH
D(7 to 0) tDS tDF
DTACK tACS tCSD tDAT
MBE741
Fig.11 MPU interface timing (WRITE cycle).
1996 Jul 08
30
Preliminary specification
SAA7185
Fig.12 Application environment of the DENC2.
handbook, full pagewidth
1996 Jul 08
+ 5 V analog 0.1 F VSSD 0.1 F VSSD 0.1 F VSSD VDDD2 VDDD3 37 DAC3 35 (1) 49 20 75 67 56 48 0.62 V (p-p) (2) CHROMA 47 50 55 54 VDDA4 VrefH II VDDA3 VDDA2 VDDA1 VSSA VSSA 0.1 F 0.1 F VSSA VSSA 0.1 F 0.1 F 15 k VSSA 0.1 F
VSSD
Philips Semiconductors
+ 5 V digital
10 H
APPLICATION INFORMATION
1 nF
10 pF X1 27.0 MHz
10 pF
(3)
3rd harmonic
XTAL1
XTAL0
VDDD1
Digital Video Encoder (DENC2)
41
40
17
VSSA DAC2 35 (1) 51 20 75 VSSA DAC1 35 (1) 53 12 75 1, 8, 19, 28, 35, 42, 62 VSSD1 to VSSD7 46 VrefL 52 VSSA
MBE734
31
1.0 V (p-p) (2) Y
digital inputs and outputs
SAA7185
1.23 V (p-p)(2) CVBS
VSSA
(1) Typical value. (2) For 100/100 colour bar. (3) Philips 12NC ordering code: 4312 065 02341.
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
PACKAGE OUTLINE PLCC68: plastic leaded chip carrier; 68 leads
SAA7185
SOT188-2
eD y 60 61 X 44 43 Z E A
eE
bp b1 wM
68
1
pin 1 index e
E
HE A A4 A1 (A 3)
k
9
27
k1
Lp detail X
10 e D HD
26 ZD B
vM A
vMB 0 5 scale 10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.30
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
24.33 24.33 23.62 23.62 25.27 25.27 1.22 1.27 24.13 24.13 22.61 22.61 25.02 25.02 1.07
45 o
0.180 inches 0.020 0.01 0.165
0.930 0.930 0.995 0.995 0.048 0.057 0.021 0.032 0.958 0.958 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.13 0.890 0.890 0.985 0.985 0.042 0.040 0.013 0.026 0.950 0.950
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT188-2 REFERENCES IEC 112E10 JEDEC MO-047AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
1996 Jul 08
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all PLCC packages. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
SAA7185
Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Jul 08
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7185
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Jul 08
34
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
NOTES
SAA7185
1996 Jul 08
35
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 708 296 8556 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 615 800, Fax. +358 615 80920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 52 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. +30 1 4894 339/911, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 648 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 83749, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 926 5361, Fax. +7 095 564 8323 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. +380 44 476 0297/1642, Fax. +380 44 476 6991 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com/ps/ (1) SAA7185_2 June 26, 1996 11:51 am SCA50
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands
657021/1200/02/pp36 Date of release: 1996 Jul 08 Document order number: 9397 750 00943

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